1. Field of the Invention
The present invention relates to a semiconductor integrated circuit and, in particular, to a logic gate circuit with a low sub-threshold leakage current.
2. Description of the Background Art
As the source voltage of a semiconductor integrated circuit is being reduced for the purpose of improving the reliability of a device and lowering the power, the threshold voltage(VT) of a MOS device is also being reduced in order to maintain operation performance. However, when the threshold voltage(VT) of the MOS device is reduced, the off-leakage current flowing through a channel of turned-off MOS devices is increased, thereby causing serious power dissipation. Therefore, many studies for reducing sub-threshold current are currently being made intensively of a circuit.
FIG. 1 illustrates a conventional logic gate circuit capable of reducing sub-threshold leakage current.
As illustrated in FIG. 1, the conventional logic gate circuit includes a main power lines (Vcc) (Vss), local power lines each connected to the main power lines (Vcc) (Vss), and an inverter 10 and a CMOS logic gate 12 each connected between the local power lines (Vcc_L) (Vss_L).
MOS devices (M1) (M2) has a high threshold voltage (High VT), and are controlled by signals (ACTb) (ACT) representing an operation state (active state) of a semiconductor memory, respectively. And, the inverter 10 including MOS devices (M3) (M4) with a low threshold voltage (Low VT) reverses an input signal (IN). The CMOS logic gate 12 performs a logic function preset according to the output of the inverter 10, for example, an inverting operation. In addition, the CMOS logic gate can be implemented so that it performs other logic functions (NAND, NOR) using the output of the inverter 10 and an external control signal (not shown).
The operation of the conventional logic gate circuit thusly configured is as follows.
During an active operation, since the signals (ACT) (ACTb) are high and low levels, respectively, the MOS devices (M1) (M2) are turned on. As the result, the main power line (Vcc) and the local power line (Vcc_L) connected with each other through the MOS device (M1) maintains the same voltage, and the main power line (Vss) and the local power line (Vss_L) connected with each other through the MOS device (M2) also maintains the same voltage. Therefore, the inverter 10 and the CMOS logic gate 12 positioned between the main power lines and the local power lines can carry out a normal operation.
During a standby operation, the MOS devices (M1) (M2) are turned off by the low and high level signals (ACT) (ACTb). Due to this, the local power lines (Vcc_L) (Vss_L) are separated from the main power lines (Vcc) (Vss), and then the inverter 10 and the CMOS logic gate 12 are influenced by the local power lines (Vcc_L) (Vss_L). Therefore, the off-current of the CMOS logic gate 12, that is, a sub-threshold leakage current occurred by the turned-off MOS devices, is restricted.
However, the conventional logic gate circuit reduces the sub-threshold leakage current by providing itself with additional signals representing an active state and standby state, as well as existing signals.
And, the conventional logic gate circuit requires a number of power lines.
In addition, the conventional logic gate has a problem that MOS devices having at least two or more threshold voltages (VT) has to be integrated in one chip.
Accordingly, it is an object of the present invention to provide a logic gate circuit for remarkably reducing sub-threshold leakage current using only existing signals.
It is another object of the present invention to provide a logic gate circuit for implementing various logic gates by combination of devices alone with a low threshold voltage.
In order to achieve the above objects, the logic gate circuit in accordance with the present invention includes a CMOS logic gate having PMOS devices and NMOS devices with a low threshold voltage, a first voltage generator applying a first reverse voltage to the PMOS device of the CMOS logic gate during a pull-down operation, and a second voltage generator outputting a second reverse voltage to the NMOS device of the CMOS logic gate during a pull-up operation.
The first voltage generator outputs a voltage greater than the source voltage by the threshold voltage to the first MOS device when the second MOS device performs a pull-down operation, and the second voltage generator outputs a voltage smaller than the earth voltage by the threshold voltage when the first MOS device performs a pull-up operation. And, the CMOS logic gate can be configured as a CMOS inverter, a NAND, or a NOR gate, and is replaceable according to the needs.
Additional advantages, objects and features of the invention will become more apparent from the description which follows.